Qualcomm, Intel and AMD at the Edge: NPUs, OpenVINO and Adaptive SoCs
Overview
NVIDIA dominates edge AI headlines, but Qualcomm, Intel and AMD together ship enormous volumes of edge-capable silicon and appear on every analyst list of edge AI market leaders. Their plays differ sharply: Qualcomm brings smartphone-derived NPUs and connectivity through its Dragonwing industrial line; Intel brings the x86 install base, Core Ultra NPUs and the OpenVINO toolkit; AMD brings Versal adaptive SoCs, Kria SOMs and XDNA NPUs in Ryzen Embedded. For buyers, the decisive question is rarely peak TOPS. It is which software ecosystem your team can actually ship on, and which vendor’s lifecycle commitments match your product’s.
Key takeaways
- Qualcomm’s Dragonwing industrial platforms span roughly 20 to several hundred vendor-stated dense TOPS across the IQ8, IQ9 and IQ10 series, with integrated connectivity as the differentiator.
- Intel’s edge story is OpenVINO: one API that schedules models across CPU, integrated GPU and the Core Ultra NPU on commodity x86 boxes.
- AMD’s Versal AI Edge and Kria SOMs pair AI engines with FPGA fabric for deterministic, I/O-heavy pipelines that fixed SoCs cannot serve.
- All three publish long embedded lifecycles, which matters for fleets planned to run 7-10 years.
- Toolchain fit beats datasheet compute: Hexagon SDK, OpenVINO and Vitis AI have very different learning curves and operator coverage.
Qualcomm: Dragonwing and the Snapdragon lineage
Qualcomm folded its industrial and embedded lines under the Dragonwing brand, reusing the Hexagon NPU architecture proven in Snapdragon phone SoCs. Public partner material describes a range from roughly 20 vendor-stated TOPS on entry parts to around 100 dense TOPS on the IQ9 series via dual NPUs, with the announced IQ10 series stated at up to 350 dense TOPS with an 18-core Oryon CPU and support for up to 20 MIPI cameras; treat top-end figures as vendor-stated until third-party benchmarks appear. Qualcomm’s separate Cloud AI 100 accelerator cards target edge servers and on-prem inference. Strengths: power efficiency inherited from mobile, integrated 5G/Wi-Fi options, and camera ISPs. The honest limits: the AI Engine Direct / Hexagon toolchain is less familiar to most CV teams than CUDA, and quantisation workflows are more prescriptive, a topic covered in our quantisation guide.
Intel: Core Ultra NPUs, OpenVINO and the Movidius lineage
Intel’s edge AI position rests on software reach rather than accelerator peaks. OpenVINO compiles models from PyTorch, TensorFlow and ONNX and schedules them across CPU cores, integrated Arc GPUs and the NPU built into Core Ultra processors through a single API, so an edge box built on a standard x86 industrial PC gets usable acceleration with no exotic hardware. The NPU lineage traces to Movidius, whose Myriad VPUs powered an earlier generation of vision sticks and cameras before being folded into the client roadmap. Strengths: zero-friction procurement (any x86 vendor), mature Linux and Windows support, and the widest pool of engineers. Limits: per-watt efficiency of a general-purpose x86 platform trails purpose-built accelerators on static CNN workloads, and headline NPU TOPS on client silicon are modest next to dedicated parts.
AMD: Versal AI Edge, Kria SOMs and Ryzen Embedded
AMD’s acquisition of Xilinx gave it the most distinctive incumbent portfolio. Versal AI Edge adaptive SoCs combine Arm cores, vector AI engines and programmable FPGA fabric, so designers can build deterministic pipelines with custom sensor interfaces (radar, LiDAR, industrial buses) alongside neural inference. Kria SOMs package the older Zynq UltraScale+ generation with a DPU overlay for cost-sensitive vision, programmed through Vitis AI. On the x86 side, Ryzen Embedded processors ship XDNA NPUs for edge PCs. Strengths: determinism, any-to-any I/O and long industrial lifecycles. Limits: FPGA-adjacent toolchains (Vitis, Vivado) demand skills most ML teams lack, and iteration is slower than a pure software flow.
Software ecosystems are the real product
All three vendors can hit competitive throughput on well-chosen workloads; what differs is the path there. OpenVINO is the gentlest on ML engineers, Hexagon rewards teams building battery or camera products at volume, and Vitis AI rewards teams with hardware engineers who need determinism. Before shortlisting on TOPS, prototype your actual model through each candidate toolchain and count the operators that fail to convert: that number predicts your integration schedule better than any benchmark, a theme developed in the selection framework.
The three incumbents compared
| Vendor | Edge platform | Architecture | Typical power band | Best fit |
|---|---|---|---|---|
| Qualcomm | Dragonwing IQ series; Cloud AI 100 | Heterogeneous SoC with Hexagon NPU | Single-digit W to 25 W+ (SoCs) | Connected, battery-sensitive and camera-dense devices |
| Intel | Core Ultra + OpenVINO | x86 CPU + integrated GPU + NPU | 15-45 W class | Edge PCs, retail and industry boxes standardised on x86 |
| AMD | Versal AI Edge, Kria SOM, Ryzen Embedded | Adaptive SoC (AI engines + FPGA fabric); x86 + XDNA | 10-75 W class | Deterministic, sensor-fusion and custom-I/O pipelines |
Where the incumbents beat the specialists, and where they do not
Choose an incumbent when procurement standardisation, long lifecycles, integrated connectivity or in-house skills dominate the decision. Specialists covered in Hailo vs Axelera vs Blaize and the specialist silicon survey generally win on inference per watt and per dollar for fixed CNN workloads, while NVIDIA Jetson wins on model flexibility. Most real fleets end up mixing tiers; the map in the landscape hub article shows where each sits.
Frequently asked questions
Is Qualcomm Dragonwing the same as Snapdragon?
Dragonwing is Qualcomm’s brand for industrial and embedded platforms, reusing the Hexagon NPU and much of the Snapdragon architecture but with industrial temperature ranges, longer lifecycles and embedded-focused SKUs rather than phone parts.
Do I need special hardware to use OpenVINO?
No. OpenVINO runs on ordinary Intel CPUs and improves as you add an integrated Arc GPU or a Core Ultra NPU. That makes it the lowest-friction starting point for teams with existing x86 edge boxes.
When does an FPGA-based platform like Versal make sense?
When the pipeline needs hard determinism, custom sensor interfaces or pre/post-processing that fixed SoCs cannot express: sensor fusion, industrial inspection with line-scan cameras, radar processing. If a standard camera-in, detections-out pipeline suffices, a fixed accelerator is simpler and cheaper.
How do these platforms handle transformers and LLMs?
All three publish transformer support in their current toolchains, with capability scaling by memory and NPU size. Qualcomm’s larger Dragonwing parts and Cloud AI 100, Intel Core Ultra via OpenVINO’s LLM runtimes, and AMD’s larger Versal and Ryzen AI parts all run quantised transformer models; verify your specific model’s operator coverage before committing.
Which incumbent has the longest supply commitment?
All three publish extended availability for embedded lines, commonly 10 years or more on industrial SKUs. Check the exact SKU’s lifecycle statement, because client-derived parts (for example consumer Core Ultra boxes) carry shorter commitments than industrial ones.
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