Axelera Metis Deep Dive: Digital In-Memory Compute for Edge Vision

Overview

The Metis AIPU from Axelera AI, a Netherlands-based semiconductor company, is an edge inference accelerator built around digital in-memory computing (D-IMC). Its published headline is a peak 214 TOPS (INT8) from a quad-core chip at a vendor-stated efficiency of roughly 15 TOPS/W, in module power envelopes running from a few watts up to low double digits depending on configuration. That combination targets one job above all: dense multi-camera machine vision on a modest power and cost budget. This deep dive explains how D-IMC works, what the published figures mean in practice, the M.2 and PCIe module options, the Voyager SDK workflow, and where a Metis module beats – or loses to – an edge GPU.

What the Metis AIPU is

Metis is a four-core AI processing unit. Each core combines a RISC-V control processor, a dataflow engine for the surrounding tensor operations, and a D-IMC matrix-vector multiplication engine that does the heavy lifting for convolutions and fully connected layers. The cores can run four independent models, cooperate on one, or be assigned per camera stream – a flexibility that matters in machine-vision boxes juggling detection, classification and OCR simultaneously. Axelera has also published SoC-style evaluation systems pairing Metis with Arm hosts such as the Rockchip RK3588, but the volume products are host-attached accelerator modules.

Digital in-memory computing, briefly

In a conventional accelerator, weights sit in SRAM or DRAM and are fetched into multiply-accumulate units; the fetching costs more energy than the arithmetic. In-memory computing collapses that distance by performing the multiply-accumulate inside the memory array itself. Analogue variants of this idea suffer from noise and drift; Axelera’s implementation is fully digital, so results are bit-exact and deterministic while still cutting most of the data movement. That is the source of the vendor-stated ~15 TOPS/W (INT8) figure and the claim – worth verifying per model – of FP32-comparable accuracy after quantisation without retraining. The approach is optimised for INT8 matrix work: it is an inference engine, not a general-purpose numeric processor.

Reading the published numbers

The 214 TOPS (INT8) figure is a peak across all four cores with the D-IMC arrays fully utilised. Real networks do not sustain peak: utilisation depends on layer shapes, resolution and how well the compiler tiles the model. More useful are Axelera’s published end-to-end throughput figures – on the order of 3,200 FPS on ResNet-50 for a single AIPU (vendor-stated) – and, better still, your own measured numbers on your own models. Power behaves the same way: a single-AIPU module is reported in roughly a 3.5-9 W band depending on utilisation and clocking, so cabinet thermal design should assume the top of the band. As always, never compare this INT8 peak against another vendor’s INT4 headline.

Form factors: M.2 to quad-AIPU PCIe

• Metis M.2 – a single AIPU on an M.2 2280 module, aimed at gateways, industrial PCs and NVRs; published peak 214 TOPS (INT8) and aggressive pricing announced from $149.
• Metis PCIe – a single-AIPU low-profile PCIe card for edge servers and industrial systems.
• Metis PCIe quad – four AIPUs on one card, published aggregate 856 TOPS (INT8), for video-analytics servers consolidating dozens of streams.
• Evaluation and compute boards through distribution partners, typically paired with x86 or Arm hosts.

All of them rely on the host for video decode unless paired with a host SoC that provides it – a real sizing consideration in high-stream-count designs.

Voyager SDK: from PyTorch to pipeline

The Voyager SDK is the compile-and-deploy stack: it imports PyTorch and ONNX models, applies post-training quantisation to INT8 against a calibration set, and generates a deployable pipeline including pre- and post-processing stages (scaling, normalisation, NMS). A model zoo covers the usual detection and classification families, and a YAML-described pipeline layer assembles multi-model, multi-stream applications. The honest caveats mirror every young toolchain: operator coverage is narrower than CUDA’s, unsupported layers fall back to the host CPU with a latency cost, and compiled performance varies materially between model families – so run your own models through the SDK before committing to fleet volumes.

Metis module line-up

Where Metis fits against a GPU

Metis-class silicon wins when the workload is fixed, quantisable INT8 vision at high stream density: city traffic analytics, retail footfall, industrial inspection cells like those in our manufacturing vision AI playbook, and NVR retrofits where an M.2 slot is the only real estate available. For Indian deployments, processing camera feeds on-site rather than streaming to cloud also keeps personal data local – a simpler posture under the DPDP Act. A GPU remains the better answer when models change weekly, need FP16, exceed the memory of an accelerator, or share a box with training and transcoding duties – the decision framework in edge AI accelerators vs GPUs applies directly, and our three-way silicon comparison positions Metis against Hailo and Blaize.

Frequently asked questions